Ceramic carriers, especially metallized ceramic (MC) carriers have been produced in large quantities and used to package integrated circuit (IC) devices. Through-hole pinning of these ceramic carriers has typically been employed to provide interconnection between the packaged IC device and the next level package.
Disclosed in the technical article by Emerick et al. titled, "Pin Insertion Into Pin Grid Arrays-Concepts, Equipment and Applications," Proc. 1991 IEEE Southern Tier Technical Conference, Oct. 25, 1991, is an MC pinning process in which a gold pin is crimped in a through-hole located in an MC carrier to provide a reliable mechanical and electrical connection between the pin and the MC carrier. Emerick et al. disclose that the manufacture of a substrate begins with a raw ceramic, which forms the backbone of the substrate. Typically the ceramic is made of an alumina composition, with the basic size and through-holes pressed and fired to final dimensions.
The metallization of the fired ceramic is accomplished by sputtering or evaporating three layers of metal, namely, a thin layer of chrome, a thicker layer of copper, and a thin layer of top chrome. The combined thickness of all three layers of metallization is approximately 7.63 microns (0.0003 inches). The metallization is photo-resist coated, exposed, developed, and etched to form a circuit pattern. Basically, all circuit lines extend from a pad in the chip site to a "donut" around each pin hole. The etch process removes the top chrome to expose copper around the pin and thus provides a solderable surface that becomes the land-to-pin connection. Once the circuitry is complete and the substrates are tested and inspected, they are then pinned by placing a pin in each hole and affixing them mechanically to the ceramic.
Shown in FIG. 1 is the final configuration that results from a conventional MC pinning process which mechanically forms a pin 10 having a pin head 14 on the circuitry side of a ceramic substrate 2 and a pin bulge 12 formed on the opposite side of ceramic substrate 2. The pins 10 connect to metal conductors 4 on the circuitry side of ceramic substrate 2 and extend out from the opposite side of ceramic substrate 2 to provide interconnection with the next board packaging level. Pins 10 may be copper or gold-plated copper depending on whether the module is designed to be plugged or soldered into the next level board.
U.S. Pat. No. 5,006,922, issued to McShane et al., discloses a ceramic pin grid array (CPGA) for packaging semiconductor devices having a single-layer ceramic base with a plurality of through-holes which are coated by an electrically conductive material such as gold, copper, silver, and their alloys. The coated through-holes are formed by applying a vacuum to the through-holes while screen printing the electrically conductive metal onto the base. Input/output pins are mechanically attached to the ceramic base by inserting and swaging the pins into the metal-lined through-holes. The swaging process mechanically forms a pin head on one side of the base and a pin bulge on the opposite side to lock the pins in place. The pins employed preferably are made of alloys of zirconium and copper plated with nickel and gold. Alternatively, McShane et al. discloses that the pins may be manufactured using other materials such as nickel- and gold-plated alloys of nickel-iron-cobalt (i.e., Kovar.RTM. alloy) or nickel-iron.
IC devices packaged using ceramic technology such as those disclosed by Emerick et al. and McShane et al. above suffer, however, from the inherent drawback that the ceramic carriers employed are susceptible to breakage during the pinning processes. Moreover, IC packages which incorporate ceramic technology are also very expensive. In order to lower packaging costs, plastic packages have been developed as an alternative to the multilayer CPGA. Plastic packages provide several important advantages for the chip operation as compared with ceramic packages, namely, higher current carrying capacity, a lower dielectric constant for shorter operational delay times, along with reduced inductance and capacitance. These plastic packages, known as plastic pin grid arrays (PPGA), provide a reliable, lower-cost packaging alternative to ceramics. These plastic packages typically employ through-hole pinning techniques, however, which incorporate lead-containing solder or pastes to mechanically secure the pins in place and to establish the required electrical connection. U.S. Pat. No. 5,102,829, issued to Cohn, discloses a process for producing a PPGA package having an encapsulated device and a heat sink forming a unitary laminate component. The PPGA includes a plurality of plated through-holes (PTHs) formed in the laminate which have a copper coating on the walls of the holes. Terminal pins made of Kovar.RTM. Ni--Fe--Co alloy or phosphor bronze are then press-fitted into the PTHs and solder-dipped to secure the pins in the holes.
The present invention overcomes the limitations, difficulties, and shortcomings of the prior art by providing a process of producing a PPGA and the product produced thereby having a gold-to-gold interconnection of pins to plated through-holes located in a laminate carrier. As a result, the present invention eliminates the need for pinning processes which incorporate lead-containing solders and pastes for attaching the pins.